Senior Signal & Power Integrity R&D Engineer

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</p><p><br>Employer: Synopsys Canada ULC<br>Position: Senior Signal &amp; Power Integrity R&amp;D Engineer<br>Terms of Employment: Permanent/Full Time<br>Location of Work: Nepean/Ottawa, Ontario<br>Salary: $110,000.00 to $120,000.00 CAD<br>Benefits: Eligible for discretionary bonuses and increases in salary. Company paid life, disability, AD&amp;D, health, dental; RRSP &amp; ESPP programs; eligibility for discretionary bonuses and salary increase<br>Hours of work: 40 hours per week/full-time<br>Contact: <a target="_blank" rel="nofollow" href="https://www.synopsys.com/company/synopsys-careers.html">https://www.synopsys.com/company/synopsys-careers.html</a></p><p>Join the Synopsys Canada team as a Senior Signal &amp; Power Integrity R&amp;D Engineer where you can explore your strong desire to learn and explore new technologies!</p><p>Duties:</p><p>• System interface interconnect review, modeling, simulating, analyzing both signal and power integrity (SIPI) effects, troubleshooting and debugging. This encompasses all aspects of physical interconnect in a system context, including both RX/TX die/silicon, package, pcb, connectors and components on multi-signal transmission line interfaces such as DDR/SERDES;<br>• Performing, verifying and documenting interface SIPI analysis outcomes as part of customer services;<br>• Completing experiments to validate modeling and methodologies;<br>• Developing and documenting SIPI requirements, flows and methodologies for internal/external customer use;<br>• Conducting micro or nanodevice simulations, characterizations, process modeling and integrations in the development of new electronic devices and products; and<br>• Investigating electrical or electronic failures.</p><p>Requirements:</p><p>• Bachelors Degree in electrical or electronics engineering or in an appropriate related engineering discipline is required, a Masters degree is considered an asset;<br>• 3-5 years of related engineering experience<br>• Working knowledge of circuit simulation tools is required as is an understanding of basic circuit and transmission line theory, familiarity with and a working knowledge of both time and frequency-domain methods of analysis and characterization<br>• Practical experience with FPGA/ASIC/SoC package and pcb design driving development improvements as per interface requirements is required;<br>• Working experience with 3rd party industry tools such as Keysight ADS, Cadence Sigrity and PowerSI, Cadence Voltus is required;<br>• Experience in at least one programming languages such as Python, TCL and Matlab is required;<br>• Die/silicon level parasitic model generation capability using Ansys Redhawk/Totem and static and dynamic EMIR analysis is required;<br>• Knowledge on interface such as DDR (e.g. DDR3, LPDDR3, DDR4 and LPDDR4), PCIe (e.g. 3 and 4), Ethernet, SATA, 56G/112G PAM4 is an asset;<br>• Familiarity with both Windows and Linux operating system is an asset; and<br>• Candidate possesses excellent communication skills, both verbal and written.</p><p>This position is a permanent full-time role, working 40 hours per week in Nepean/Ottawa, Ontario. Salary to be negotiated $110,000 to $120,000 CAD with eligibility for discretionary bonuses and salary increases. Offered group benefits included life, disability, extended health, vision, dental, RRSP.</p>

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